As electronic products are being developed in ways that make them lighter, thinner, smaller and more multi-functional, the functions of chips and packages are increasing. The demand for high-density circuit will be unavoidable. The shrinkage of line pitch has become a major challenge. Traditional metallization processes for fine pitch metal include conducting-layer deposition, lithography, electroplating, and etching. The whole process uses up a lot of materials, chemical solvents and water resources. Therefore, the harm being done to the environment is a worry for the future development of the electronics industry.
A semi-additive method is currently used in the metallization process. The barrier/seed layer is deposited by a physical vapor deposition (PVD) method. After formation of the circuit, a wet etching process is used to remove the unwanted barrier and/or seed layer.
As the pitch of the circuit shrinks, incomplete etching or over-etching may be cause issues with reliability and yield.
Accordingly, a novel metallization structure for the current field of patterned metallization of fine pitch circuit is called for.